A complex programmable logic device, or CPLD, typically includes two or more “function blocks” connected together and to input/output (I/O) resources by an centralized interconnect structure. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
FIG. 1 is a simplified illustration of a CPLD. A CPLD typically includes two or more function blocks (FBs 101a–101h) connected together and to input/output (I/O) blocks (I/Os 102a–102f) by a centralized interconnect structure (CIS) 103. Centralized interconnect structure 103 includes many programmable multiplexers 105, each including several programmable interconnect points (PIPs) 104 (designated in the figures by small circles). FIG. 1A illustrates how a group of PIPs 105 can be combined to form a programmable multiplexer. In each multiplexer 105, only one PIP 104 is enabled. The enabled PIP selects one of the many input signals provided to the centralized interconnect structure, and the selected input signal is provided as the output signal OUT from programmable multiplexer 105.
Each function block includes one or more macrocells. A macrocell is a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. FIG. 2 is a block diagram of a function block from one known CPLD, the CoolRunner®-II CPLD from Xilinx, Inc. The function block includes a PLA array and 16 macrocells MC1–MC16. The PLA array is driven by 40 input signals from a centralized interconnect structure (CIS). Each macrocell provides one output signal, which is provided to one of the I/O blocks (IOBs) and also returns to the centralized interconnect structure CIS to provide one of the input signals (see FIG. 1). Therefore, each function block has 40 data inputs and 16 data outputs. Each macrocell also receives several global signals, including a global set/reset signal and three global clock signals.
Further information on Xilinx CPLDs can be found in pages 6–1 through 6–60 of the Xilinx 2000 Data Book entitled “The Programmable Logic Data Book 2000”, published in 2000 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
Practically speaking, the number of function blocks in a traditional CPLD is inherently limited by the size of the centralized interconnect structure. Increasing the size of the centralized interconnect structure above a certain threshold increases the CPLD die size dramatically. One method that has been suggested to overcome this limitation is to apply a hierarchical approach, dividing the logic in the centralized interconnect structure into several logic levels. This approach does reduce the die size, but the signal delay through the multiple logic levels leads to performance degradation.
Therefore, it is desirable to provide a new CPLD architecture that allows a CPLD to be scaled in logic capacity without an unacceptable increase in die size or signal delays.